The present disclosure relates to a multilayer ceramic capacitor and a board having the same.
In accordance with the recent trend toward miniaturization and high capacitance of electronic products, a demand for miniaturization and high capacitance of electronic components used in electronic products has increased.
In the case of a multilayer ceramic capacitor, when equivalent series inductance (ESL) increases, performance of an electronic product may deteriorate. Moreover, as the electronic component becomes miniaturized and has high capacitance, an influence of an increase in ESL of the multilayer ceramic capacitor on deterioration of performance of the electronic component becomes greater.
Particularly, in accordance with increasingly high performance of an integrated circuit, use of a decoupling capacitor is increasing. Therefore, a demand is rising for a multilayer ceramic capacitor (MLCC) having a 3-terminal vertical structure, so-called “low inductance chip capacitor (LICC)” capable of reducing inductance of the capacitor by reducing a distance between external terminals to decrease a current flow path.